1. Field of the Invention
The present invention relates to a layout pattern verification apparatus for verifying surge breakdown resistance in the layout pattern of a semiconductor integrated circuit.
2. Description of the Background Art
FIG. 28 is a block diagram showing the structure of a conventional layout pattern verification apparatus. Referring to FIG. 28, a layout information extraction module 101 incorporates layout pattern data 151 and a layout information extraction rule 152, and outputs layout information 153 to a design rule verification module 102. The layout pattern data 151 define the structure of a semiconductor integrated circuit (IC), while the layout information extraction rule 152 stores a device recognition rule, circuit connection information as to types and manners of connection of devices and the like in a rule system. The layout information 153 is obtained by adding device information, the circuit connection information and the like to the layout pattern data 151.
The design rule verification module 102 incorporates the layout information 153 and the verification rule 154, and outputs verification result information based on the verification rule 154 with respect to the layout information 153 to a verification result output module 103. The verification rule 154 defines reference values for geometrically verifying various values such as formation widths of devices on the layout pattern, device spaces and the like.
On the basis of the verification result information obtained from the design rule verification module 102, the verification result output module 103 outputs verification result display data 155 to a display module 104 such as a display unit, to graphically display the verification result on the display module 104.
FIG. 29 is a flow chart showing a verification operation of the layout pattern verification apparatus shown in FIG. 28.
Referring to FIG. 29, the layout information extraction module 101 incorporates the layout pattern data 151 and the layout information extraction rule 152 and outputs the layout information 153, which is obtained by adding device information, circuit connection information and the like to the layout pattern data 151 on the basis of the layout information extraction rule 152, to the design rule verification module 102 at a step S101.
At a step S102, the design rule verification module 102 incorporates the layout information 153 and the verification rule 154, verifies a geometric design rule on a layout pattern defined by the layout information 153 on the basis of the verification rule 154, and outputs verification result information to the verification result output module 103.
At a step S103, the verification result output module 103 outputs the verification result display data 155 to the display module 104 on the basis of the verification result information obtained at the step S102, thereby displaying the verification result display data 155 on the display module 104.
The conventional layout pattern verification apparatus having the aforementioned structure merely verifies the layout pattern on the basis of the common geometric verification rule and reference values defined by the verification rule 154 with respect to the layout pattern to be verified.
In order to verify surge breakdown resistance for recognizing the degree of occurrence of surge breakdown in an integrated circuit, it is necessary to direct attention to input and output circuit parts of the integrated circuit and apply a specific geometric design rule to the input and output circuit parts.
As hereinabove described, however, the conventional layout pattern verification apparatus uniformly verifies the layout pattern in every portion of the integrated circuit, and applies no specific geometric design rule to the input and output circuit parts.
Therefore, presence/absence of surge breakdown must be visually verified through a display of the layout pattern or the like. Thus, accuracy of such verification depends on the verifier, leading to dispersion and frequent verification errors.
Thus, the conventional layout pattern verification apparatus performs absolutely no surge breakdown verification.